Pipelined MIPS Simulator
Converted an unpipelined MIPS processor simulator written in C into a 5-stage pipelined simulator with explicit IF, ID, EX, MEM, and WB pipeline registers. Implemented core pipeline behavior including data forwarding, load-use stalls, branch/jump handling with pipeline flushes, and correct write-back/memory behavior, while preserving architectural rules like keeping R0 constant and checking for invalid memory accesses. The simulator assembled and executed a small MIPS-like instruction set including arithmetic, loads/stores, branches, and jumps, and reported execution statistics such as cycle count, IPC, and CPI.